Semiconductor chip package comprising substrate, semiconductor chip, and leadframe and a method for fabricating the same

ABSTRACT

A semiconductor chip package may comprise a semiconductor chip disposed on a substrate. The semiconductor chip may have a first surface and a second surface. The first surface of the semiconductor chip may be connected to the substrate. The semiconductor chip package may comprise a leadframe that includes a first lead and a second lead. The first lead of the leadframe may be directly attached to the second surface of the semiconductor chip. The second lead of the leadframe may be directly attached to the substrate.

TECHNICAL FIELD

The present disclosure relates to a semiconductor chip package, anelectronic module, and a method for fabricating a semiconductor chippackage.

BACKGROUND

In many electronic systems it is necessary to employ converters likeDC/DC converters, AC/DC converters, or DC/AC converters in order togenerate the currents and voltages to be used by an electronic circuit.A buck converter typically comprises one or more half-bridge circuits,each provided by two semiconductor power switches, such as power MOSFETdevices, and further components such as diodes, inductors, andcapacitors. An important aspect in development of these types ofsemiconductor chip packages is improvement of the connections betweenthe different components within the package.

SUMMARY

According to some possible implementations, a semiconductor chippackage, may include: a semiconductor chip disposed on a substrate,wherein the semiconductor chip has a first surface and a second surface,and wherein the first surface of the semiconductor chip is connected tothe substrate; and a leadframe that includes a first lead and a secondlead, wherein the first lead of the leadframe is directly attached tothe second surface of the semiconductor chip, and wherein the secondlead of the leadframe is directly attached to the substrate.

According to some possible implementations, a method for fabricating asemiconductor chip package may include: disposing a semiconductor chipon a substrate, wherein the semiconductor chip has a first surface and asecond surface, and wherein the first surface of the semiconductor chipis connected to the substrate; attaching a first lead of a leadframe tothe second surface of the semiconductor chip; and attaching second leadof the leadframe to the substrate.

According to some possible implementations, an electronic module mayinclude: at least one semiconductor chip package comprising: asemiconductor chip disposed on a substrate, wherein a first surface ofthe semiconductor chip is connected to the substrate; and a leadframethat includes a first lead and a second lead, wherein the first lead ofthe leadframe is directly attached to a second surface of thesemiconductor chip, and wherein the second lead of the leadframe isdirectly attached to the substrate.

The person skilled in the art recognizes additional features andadvantages upon reading the following detailed description and upongiving consideration to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of examples and are incorporated in and constitute a partof this specification. The drawings illustrate examples and togetherwith the description serve to explain principles of examples. Otherexamples and many of the intended advantages of examples will be readilyappreciated as they become better understood by reference to thefollowing detailed description.

The elements of the drawings are not necessarily to scale relative toeach other. Like reference numerals designate corresponding similarparts.

FIGS. 1A and 1B show a schematic cross-sectional side viewrepresentation and a top view representation, respectively, of asemiconductor chip package according to an example in which a first leadis attached to a semiconductor chip and a second lead is attached to asubstrate.

FIGS. 2A-2C show a schematic cross-sectional side view representation ofa semiconductor chip package, a top view representation of asemiconductor chip package, and a circuit diagram of an electricalcircuit, respectively, according to an example in which a first lead isattached to first and second semiconductor chips and a second lead isattached to a substrate.

FIGS. 2D and 2E show a top view representation of a semiconductor chippackage and a circuit diagram of an electrical circuit, respectively,according to another example in which example a first lead is attachedto first, second, and third semiconductor chips and a second lead isattached to a substrate.

FIGS. 3A and 3B and show a schematic cross-sectional side viewrepresentation and a top view representation, respectively, of asemiconductor chip package according to an example in which a first leadis attached to first and second semiconductor chips and a second lead isattached to a substrate, wherein the first and second leads are providedwith additional features in order to enhance the stability of theconnections.

FIG. 4 shows a flow diagram for illustrating a method for fabricating asemiconductor chip package as described herein.

FIGS. 5A-5F show schematic cross-sectional side view representationsassociated with an example of the method for fabricating a semiconductorchip package of FIG. 4.

FIGS. 6A and 6B show a schematic top view representation of asemiconductor chip package and a circuit diagram of an electricalcircuit, respectively, according to another example in which foursemiconductor chips are included in a semiconductor package in order toform a half-bridge circuit.

FIGS. 7A and 7B show a schematic top view representation and a schematiccross-sectional side view representation, respectively, of an exampleelectronic module that comprises six semiconductor chip packages, asdescribed herein.

DETAILED DESCRIPTION

The aspects and examples are now described with reference to thedrawings, wherein like reference numerals are generally utilized torefer to like elements throughout. In the following description, forpurposes of explanation, numerous specific details are set forth inorder to provide a thorough understanding of one or more aspects of theexamples. It may be evident, however, to one skilled in the art that oneor more aspects of the examples may be practiced with a lesser degree ofthe specific details. In other instances, known structures and elementsare shown in schematic form in order to facilitate describing one ormore aspects of the examples. It is to be understood that other examplesmay be utilized and structural or logical changes may be made withoutdeparting from the scope of the present disclosure. It should be notedfurther that the drawings are not to scale or not necessarily to scale.

In the following detailed description, reference is made to theaccompanying drawings, which form a part hereof, and in which is shownby way of illustration specific aspects in which the disclosure may bepracticed. In this regard, directional terminology, such as “top”,“bottom”, “front”, “back” etc., may be used with reference to theorientation of the figures being described. Since components ofdescribed devices may be positioned in a number of differentorientations, the directional terminology may be used for purposes ofillustration and is in no way limiting. It is understood that otheraspects may be utilized and structural or logical changes may be madewithout departing from the scope of the present disclosure. Thefollowing detailed description, therefore, is not to be taken in alimiting sense, and the scope of the present disclosure is defined bythe appended claims.

In addition, while a particular feature or aspect of an example may bedisclosed with respect to only one of several implementations, suchfeature or aspect may be combined with one or more other features oraspects of the other implementations as may be desired and advantageousfor any given or particular application. Furthermore, to the extent thatthe terms “include”, “have”, “with” or other variants thereof are usedin either the detailed description or the claims, such terms areintended to be inclusive in a manner similar to the term “comprise”.

The terms “coupled” and “connected”, along with derivatives may be used.It should be understood that these terms may be used to indicate thattwo elements co-operate or interact with each other regardless whetherthey are in direct connection with each other, or whether they are notin direct connection with each other. A direct connection can have themeaning of a positive or form-fitting connection of two elements. Also,even if two elements are described to be in direct connection with eachother, there can still be a layer like, for example, a solder layer, asinter layer or a glue layer between the two elements, which layer hasonly the function of effectuating and ensuring the connection betweenthe two elements.

The semiconductor chip package according to one aspect comprises asubstrate comprising an insulator layer covered with metallic layers onboth of its main surfaces. According to an example, the insulator layermay comprise a ceramic material. According to a further example, thesubstrate can be a direct copper bonded (DCB) substrate, a directaluminum bonded (DAB) substrate, or an active metal brazing (AMB)substrate. According to another example, the substrate can be aninsulated metal substrate (IMS).

The examples of a semiconductor chip package comprise a firstsemiconductor chip which may comprise a transistor device. Thetransistor device may comprise a MOS transistor structure, a bipolartransistor structure or an IGBT (insulated gate bipolar transistor)structure of either polarity NPN or PNP, wherein those structures may beprovided in a form in which at least one electrical contact element isarranged on a first main face of the semiconductor die and at least oneother electrical contact element is arranged on a second main faceopposite to the first main face of the semiconductor die (verticaltransistor structures).

Notably, any of the semiconductor chip packages described herein may beassociated with (e.g., included in) a power semiconductor product oranother type of product that uses relatively high currents (e.g., ascompared to a product that uses relatively low currents, such as asensor, a microcontroller, and/or the like). For example, the leadframeconfigurations described herein may be used in place of wirebonding,which has difficulties carrying relatively large current densities, mayresult in damage to a semiconductor chip (e.g., when thick wirebonds areused), and/or may be cost prohibitive. In some implementations, thesemiconductor chip(s), associated with a semiconductor chip packagedescribed herein, may be a power switch.

FIGS. 1A and 1B show a schematic cross-sectional side viewrepresentation and a top view representation, respectively, of asemiconductor chip package 10 according to an example in which a firstlead is attached to a semiconductor chip and a second lead is attachedto a substrate. The cross-sectional view of FIG. 1A has been taken alonga plane indicated by line A-A in FIG. 1B.

The semiconductor chip package 10 comprises a substrate 11 comprising aninsulator layer 11A and a first metallic layer 11B disposed on a firstupper main face of the insulator layer 11A, and a second metallic layer11C disposed on a second lower main face of the insulator layer 11A.According to an example, the substrate 11 can be a direct bonded copper(DCB) wherein the insulator layer 11A comprises a ceramic material, andthe first and second metallic layers 11B and 11C are comprised of copperlayers.

The semiconductor chip package 10 further comprises a firstsemiconductor chip 12 comprising a first surface (e.g., an upper mainface) and a second surface (e.g., a lower main face), a first contactpad (not shown) disposed on the first surface, and a second contact pad(not shown) disposed on the second surface, wherein the firstsemiconductor chip 12 is disposed on the first metallic layer 11B of thesubstrate 11.

The semiconductor chip package 10 of FIG. 1 further comprises aleadframe 13 comprising a first lead 13.1 and a second lead 13.2,wherein the first lead 13.1 is attached to the first contact pad of thesemiconductor chip 12 (e.g., such that the first lead 13.1 is connectedto the first surface of the semiconductor chip 12 via the first contactpad), and the second lead 13.2 is attached to the first metallic layer11B of the substrate 11.

The semiconductor chip package 10 of FIG. 1 further comprises anencapsulant 14 disposed on the substrate 11, the first semiconductorchip 12, and the leadframe 13.

As shown in the example of FIG. 1, the first lead 13.1 can be attachedto the first contact pad of the semiconductor chip 12, and the secondlead 13.2 can be the first metallic layer 11B of the substrate 11. Suchattachment may be referred to herein as direct attachment. Theattachments can be formed by, for example, soldering, sintering, orglue-die attach, which means that a solder layer, a sinter layer, or aglue layer can be provided between the first and second leads 13.1 and13.2 and the semiconductor chip 12 and the substrate 11, respectively.

The semiconductor chip 12 can be a semiconductor transistor chip havinga vertical structure, in particular an insulated gate bipolar transistor(IGBT) chip. The first contact pad of the semiconductor chip 12 can thusbe an emitter contact pad located at the first surface of thesemiconductor chip 12, and can be attached to the first lead 13.1. Thesecond contact pad can be a collector contact pad located at the secondsurface of the semiconductor chip 12, and can be attached to the firstmetallic layer 11B of the substrate 11. The semiconductor chip 12 isthus connected in series between the first and second leads 13.1 and13.2.

In some implementations, as shown in FIGS. 1A and 1B, the first lead13.1 and the second lead 13.2 may each include a single lead.Alternatively, the first lead 13.1 and/or the second lead 13.2 may eachinclude two or more leads, as will be shown in further examples below.

According to the example shown in FIGS. 1A and 1B, the first and secondleads 13.1 and 13.2 are disposed on opposing side faces of thesemiconductor chip package 10. It is, however, also possible to locatethe first and second leads 13.1 and 13.2 at the same side face of thesemiconductor chip package or at two adjacent side faces of thesemiconductor chip package.

The material of the encapsulant 14 can be an electrically insulatingmaterial, such as a molding material, a resin material, or an epoxymaterial. The encapsulating material may also comprise one or more ofthe above-mentioned materials and, in some implementations, may includefiller materials embedded therein, such as thermally conductiveincrements. These filler increments can be made of, for example, AlO orAl2O3, AlN, BN, or SiN.

As shown in the example of FIG. 1, the encapsulant 14 can be applied insuch that the encapsulant 14 comprises a first lower main face and asecond upper main face opposite to the first main face, and four sidefaces connecting the first and second main faces, wherein the first andsecond leads 13.1 and 13.2 extend through one or more of the side facesof the encapsulant 14. The first lower main face of the encapsulant 14can be coplanar with the lower main face of the substrate 11 (i.e., withthe lower main face of the second metallic layer 11C of the substrate11).

The leadframe 13 may comprise further leads which, for purposes ofclarity and simplicity, are not shown in FIGS. 1A and 1B and which maybe connected with further contact pads of the semiconductor chip 12.There will be shown below further examples of semiconductor chippackages in which these further connections will be depicted.

The number, arrangement, thicknesses, and/or the like, of layers andelements shown in FIGS. 1A and 1B are provided as an example. Inpractice, the semiconductor chip package 10 may include additionallayers and/or elements, fewer layers and/or elements, different layersand/or elements, or differently arranged layers and/or elements thanthose shown in FIGS. 1A and 1B.

FIGS. 2A-2C show a schematic cross-sectional side view representation ofa semiconductor chip package 20, a top view representation of thesemiconductor chip package 20, and a circuit diagram of an electricalcircuit, respectively, according to an example in which a first lead isconnected to first and second semiconductor chips and a second lead isconnected to a substrate. The cross-sectional view as shown in FIG. 2A,has been taken along a plane indicated by line A-A in FIG. 2B.

The semiconductor chip package 20 comprises a substrate 21 which can besimilar to the substrate 11 of the semiconductor chip package 10, namelycomprising an insulator layer 21A covered by first and second metalliclayers 21B and 21C on its upper and lower main faces.

The semiconductor chip package 20 further comprises a firstsemiconductor chip 22 which can be similar to the semiconductor chip 12of the semiconductor chip package 10 and can likewise be attached withits second contact pad on its second surface (e.g., a lower main face)to the metallic layer 21B of the substrate 21.

The semiconductor chip package 20 further comprises a secondsemiconductor chip 25 which may comprise a first contact pad at a firstsurface (e.g., an upper main face) and a second contact pad at a secondsurface (e.g., a lower main face). The second semiconductor chip 25 can,for example, be a semiconductor diode chip which is connected with itssecond contact pad with the metallic layer 21B of the substrate 21.

The semiconductor chip package 20 further comprises a leadframe 23comprising first leads 23.1 and second leads 23.2 (e.g., two separatefirst leads 23.1 and two separate second leads 23.2). The first leads23.1 are attached to the upper electrical contact pads of the first andsecond semiconductor chips 22 and 25, respectively. In someimplementations, as shown in FIG. 2B, the first lead 23.1 includes atleast two leads that are aligned along substantially parallel directions(e.g., within approximately 5°). In particular, the first leads 23.1 areattached to the emitter contact pad 22.1 of the semiconductor transistorchip 22 and with the anode contact 25.1 of the semiconductor diode chip25. The second leads 23.2 are attached to the first upper metallic layer21B of the substrate 21. In some implementations, as shown in FIG. 2B,the second lead 23.2 includes at least two leads that are aligned alongsubstantially parallel directions (e.g., within approximately 5°).

Here, the first and second semiconductor chips 22 and 25 areelectrically connected in parallel between the first and second leads23.1 and 23.2. If the first semiconductor chip 22 is a semiconductortransistor chip and the second semiconductor chip 25 is a semiconductordiode chip, then a circuit configuration is provided which is depictedin the circuit diagram of FIG. 2C. The circuit diagram shows thetransistor 22 (e.g., included in the semiconductor transistor chip 22),and the diode 25 (e.g., included in the semiconductor diode chip 25). Insome implementations, the diode 25 is provided to protect the transistor22 against unwanted and unintentionally occurring peak voltages.

The cross-sectional view of FIG. 2A shows the connections between theelements in somewhat more detail. More specifically, the first andsecond semiconductor chips 22 and 25 are attached to the upper metalliclayer 21B of the substrate 21 by means of a layer, in particular asolder layer, a sinter layer or a glue layer. The material of such alayer can be the same for the connections of the first and secondsemiconductor chips 22 and 25. In the case of soldering, a first soldermaterial can be used for attaching the first and second semiconductorchips 22 and 25 to the upper metallic layer 21B of the substrate 21.Furthermore, layers are shown that connect the first leads 23.1 to thefirst upper contact pads of the first and second semiconductor chips 22and 25, and a layer is shown that connects the second leads 23.2 to theupper metallic layer 21B of the substrate 21. Again, in the case ofsoldering, a second solder material can be used for these connections.The first and second solder materials may be different from each other,as described below.

The cross-sectional view of FIG. 2A also shows that both the first andsecond leads 23.1 and 23.2 comprise particular shapes that allow them tobe connected to the first and second semiconductor chips 22 and 25 andthe substrate 21, respectively. More specifically, the first leads 23.1each comprise a first horizontal portion 23.1A nearer to a side face ofthe encapsulant 24, a second horizontal portion 23.1B nearer to a middleof the first lead 23.1, and a third horizontal portion 23.1C nearer toan end of the first lead 23.1, and deflections between the firsthorizontal portion 23.1A and the second horizontal portion 23.1B, andbetween the second horizontal portion 23.1B and the third horizontalportion 23.1C. The second and third horizontal portions 23.1B and 23.1Cmay be provided to make contact with their lower faces with the uppercontact pads of the first and second semiconductor chips 22 and 25.Hence, the second and third horizontal portions 23.1B and 23.1C may beprovided essentially on the same level if the first and secondsemiconductor chips 22 and 25 have equal thicknesses. The firsthorizontal portion 23.1A may have a higher level than the second andthird horizontal portions 23.1B and 23.1C as the lead 23.1 has to bebent down from the first horizontal portion 23.1A down to the secondhorizontal portion 23.1B.

The second leads 23.2 may each comprise a first horizontal portion 23.2Anearer to a side face of the encapsulant 24 and a second lowerhorizontal portion 23.2B which makes contact with the upper metalliclayer 21B of the substrate 21.

The leadframe 23 of the semiconductor chip package 20 of FIG. 2 mayfurther comprise third leads 23.3 in order to make electrical contactwith further contact pads of the first semiconductor chip 22. Morespecifically, in case of the first semiconductor chip 22 being an IGBTchip, the IGBT chip may comprise, on the first surface, an emittercontact pad 22.1, a gate contact pad 22.2, an emitter-sense contact pad22.3, and/or the like. In this case the third leads 23.3 may include twothird leads 23.3, one of which is electrically connected with the gatecontact pad 22.2 and the other of which is electrically connected withthe emitter-sense contact pad 22.3, whereas the first leads 23.1 areattached to the emitter contact pad 22.1 of the first semiconductor chip22 and the anode contact pad of the diode 25.1, as described above. Boththird leads 23.3 may be embedded in the encapsulant 24 in a mannersimilar to that of the first and second leads 23.1 and 23.2, and mayextend through a side face of the encapsulant 24. In the example shownin FIG. 2B, the third leads 23.3 extend through the same side face ofthe encapsulant 24 as the first leads 23.1. It is likewise possible thatthe third leads 23.3 extend through any other one of the side faces ofthe encapsulant 24.

The third leads 23.3 can be connected via bond wires 26 with the gatecontact pad 22.2 and the emitter-sense contact pad 22.3. Instead of bondwires, clips could be used for making the connections, wherein the clipscould be soldered to the contact pads 22.2 and 22.3 and the third leads23.3.

FIGS. 2D and 2E show a top view representation of a semiconductor chippackage 28 and a circuit diagram of an electrical circuit, respectively,according to another example in which example a first lead is attachedto first, second, and third semiconductor chips and a second lead isattached to a substrate.

Similar to the semiconductor chip package 20, the semiconductor chippackage 28 comprises a substrate 21. As shown in FIG. 2D, thesemiconductor chip package 28 further comprises a first semiconductorchip 22A (e.g., a first semiconductor transistor chip), a secondsemiconductor chip 22B (e.g., a second semiconductor transistor chip),and a third semiconductor chip 25 (e.g., a semiconductor diode chip),each of which can be attached to the substrate 21.

The semiconductor chip package 20 further comprises a leadframe 23comprising first leads 23.1 and second leads 23.2 (e.g., two separatefirst leads 23.1 and two separate second leads 23.2). The first leads23.1 are attached to the upper electrical contact pads of the firstsemiconductor chip 22A, the second semiconductor chip 22B, and the thirdsemiconductor chip 25. In some implementations, as shown in FIG. 2D, thefirst lead 23.1 includes at least two leads that are aligned alongsubstantially parallel directions (e.g., within approximately 5°). Inparticular, the first leads 23.1 are attached to the emitter contact pad22.1 of the first semiconductor chip 22A, the emitter contact pad 22.1of the second semiconductor chip 22B, and the anode contact 25.1 of thethird semiconductor chip 25. The second leads 23.2 are attached to thefirst upper metallic layer 21B of the substrate 21. In someimplementations, as shown in FIG. 2B, the second lead 23.2 includes atleast two leads that are aligned along substantially parallel directions(e.g., within approximately 5°).

Here, the first semiconductor chip 22A, the second semiconductor chip22B, and the third semiconductor chip 25 are electrically connected inparallel between the first and second leads 23.1 and 23.2. If the firstsemiconductor chip 22A is a first semiconductor transistor chip, thesecond semiconductor chip 22B is a second semiconductor transistor chip,and the third semiconductor chip 25 is a semiconductor diode chip, thena circuit configuration is provided which is depicted in the circuitdiagram of FIG. 2E. The circuit diagram shows the transistor 22A (e.g.,included in the first semiconductor transistor chip 22A), the transistor22B (e.g., included in the second semiconductor transistor chip 22B),and the diode 25 (e.g., included in the semiconductor diode chip 25). Insome implementations, the diode 25 is provided to protect thetransistors 22A and 22B against unwanted and unintentionally occurringpeak voltages.

In cross section, the connections between the elements may be similar tothose as described above in connection with the semiconductor chippackage 20.

In some implementations, the first and second leads 23.1 and 23.2comprise particular shapes that allow them to be connected to the firstsemiconductor chip 22A, the second semiconductor chip 22B, and the thirdsemiconductor chip 25 and the substrate 21, as described above.

The number, arrangement, thicknesses, and/or the like, of layers andelements shown in FIGS. 2A-2E are provided as examples. In practice, thesemiconductor chip package 20 and/or the semiconductor chip package 28may include additional layers and/or elements, fewer layers and/orelements, different layers and/or elements, or differently arrangedlayers and/or elements than those shown in FIGS. 2A-2E.

FIGS. 3A and 3B and show a schematic cross-sectional side viewrepresentation and a top view representation, respectively, of asemiconductor chip package 30 according to an example in which a firstlead is attached to first and second semiconductor chips and a secondlead is attached to a substrate, wherein the first and second leads areprovided with additional features in order to enhance the stability ofthe connections. The cross-sectional view as shown in FIG. 3A, has beentaken along a plane indicated by line A-A in FIG. 3B.

The semiconductor chip package 30 is similar to the semiconductor chippackage 20, in particular with regard to the substrate 31 comprisinginsulator layer 31A and first and second metallic layers 31B and 31C,first and second semiconductor chips 32 and 35 and their respectiveconnections with the first metallic layer 31B, the encapsulant 34disposed on the substrate 31, and the leadframe 33 comprising first,second, and third leads 33.1, 33.2, and 33.3. The shape andconfiguration of the first and second leads 33.1 and 33.2, however, isdifferent from the first and second leads 23.1 and 23.2 of the leadframe23 of the semiconductor chip package 20. More specifically, the firstand second leads 33.1 and 33.2 comprise additional features whichfurther improve the connections to the first and second semiconductorchips 32 and 35 and the substrate 31.

As shown, the first lead 33.1 differs from the first lead 23.1 of FIG. 2in that it extends beyond the first contact pad 32.1 of the firstsemiconductor chip 32 to the left (see FIG. 3B) and is then bentdownwards onto the first metallic layer 31B of the substrate 31 (seeFIG. 3A). As can be seen in FIG. 3B, the left end portions of the firstleads 33.1 may extends below the upper surfaces of the firstsemiconductor chip 32 and the second semiconductor chip 35. In somecases, the left end portions of the first leads 33.1 may extend suchthat these portions rest on an island 31B.1 (e.g., a copper island)formed in the first metallic layer 31B, wherein the island 31B.1 isformed by etching a trench 31B.2 into the upper metallic layer 31B. Inthis way, a short-circuit between the emitter and collector of the firstsemiconductor chip 32 is avoided. The left end portions of the firstleads 33.1 rest on and/or may be pressed against the first upper layer31B and, thus, strengthen the connection of the first leads 33.1 to thefirst surface of the first semiconductor chip 32. In someimplementations, after the encapsulant 34 is disposed on thesemiconductor chip package 30, the left end portions of the first leads33.1 may rest substantially on the substrate 31, meaning that one ormore of the left end portions of the first leads 33.1 may rest on thesubstrate 31 and/or on a portion of the encapsulant 34 that flowsbetween the left end portions and the substrate 31. In such a case, athickness of the portion of the encapsulant 34 between the left endportions and the substrate 31 may be, for example, less than or equal toapproximately 100 micrometers (μm).

Furthermore, the second leads 33.2 are connected to the first metalliclayer 31B of the substrate 31 by a layer 37, which can be a solderlayer, a sinter layer, a glue layer, and/or the like. The thickness ofthe layer 37 can be equal to, smaller than, or greater than thethickness of the second leads 33.2. The second leads 33.2 extend beyondthe layer 37 to the right (see FIG. 3B) and are then bent downward sothat the second leads 33.2 rest on the first metallic layer 31B (seeFIG. 3A). The right end portions of the second leads 33.2 thus rest onand/or are pressed against the first metallic layer 31B such that theconnections between the second leads 33.2 and the first metallic layer31B are improved. In some implementations, after the encapsulant 34 isdisposed on the semiconductor chip package 30, the right end portions ofthe second leads 33.2 may rest substantially on the substrate 31,meaning that one or more of the right end portions of the second leads33.2 may rest on the substrate 31 and/or on a portion of the encapsulant34 that flows between the right end portions and the substrate 31. Insuch a case, a thickness of the portion of the encapsulant 34 betweenthe left end portions and the substrate 31 may be, for example, lessthan or equal to approximately 100 μm.

FIG. 3B also shows the gate contact pad 32.2 and the emitter-sensecontact pad 32.3 which can be similar to the respective contact pads22.2 and 22.3 of the semiconductor chip package 20.

FIG. 3A shows that the first leads 33.1 may comprise horizontal portions33.1A, 33.1B, and 33.1C similar to the respective horizontal portions23.1A, 23.1B, and 23.1C as shown in FIG. 2A. Likewise the second leads33.2 may comprise horizontal portions 33.2A and 33.2B similar to therespective horizontal portions 23.2A and 23.2B as shown in FIG. 2.

It has already been mentioned above that the various connections betweenthe chips and the substrate and between the leads and the chips and thesubstrate can be realized by soldered layers, sintered layers, gluelayers, and/or the like. It should be added herewith that also a mix ofdifferent types of connection layers through the semiconductor chippackage is possible. For example, the one or more semiconductor chipscould be sintered to the first metallic layer of the substrate, and thefirst and second leads could be soldered to the one or more chips andthe first metallic layer of the substrate.

The number, arrangement, thicknesses, and/or the like, of layers andelements shown in FIGS. 3A and 3B are provided as examples. In practice,the semiconductor chip package 30 may include additional layers and/orelements, fewer layers and/or elements, different layers and/orelements, or differently arranged layers and/or elements than thoseshown in FIGS. 3a and 3B.

FIG. 4 shows a flow diagram for illustrating a method for fabricating asemiconductor chip package as described herein.

The method 40 of FIG. 4 comprises providing a substrate comprising, forexample, an insulator layer and a first metallic layer disposed on afirst upper main face of the insulator layer, and a second metalliclayer disposed on a second lower main face of the insulator layer (41).As previously indicated and shown in the above examples, the substratecan be DCB in some implementations.

The method 40 further comprises providing a first semiconductor chipcomprising a first surface (e.g., an upper main face) and a secondsurface (e.g., a lower main face) (42). In some implementations, a firstcontact pad may be disposed on the first surface, and a second contactpad may be disposed on the second surface. The first semiconductor chipcan be a transistor chip having a vertical structure, such as an IGBTchip wherein the first contact pad is an emitter contact pad, and thesecond contact pad is a collector contact pad.

The method 40 further comprises disposing the first semiconductor chipon the substrate (43). This can be done, for example, by soldering,sintering, glue die attach, and/or the like. In case of soldering, asolder layer can be applied onto the upper surface of the first metalliclayer by, for example, dispensing.

The method 40 further comprises providing a leadframe comprising a firstlead and a second lead (44). The leadframe can be formed like one ormore of the leadframes 13, 23, or 33 as described above. In someimplementations, the leadframe may comprise at least two first leads andtwo second leads. In some implementations, the first and second lead orleads may be positioned at opposing side faces of the package to befabricated.

The method 40 further comprises attaching the first lead to the firstsemiconductor chip (45). The attaching can be performed by, for example,soldering, sintering, glue die attaching, and/or the like. In the caseof soldering, a solder layer can be applied onto the first contact padof the first semiconductor chip and the first lead (e.g., a horizontalportion of the first lead) can be soldered onto the first contact pad bya solder reflow process.

The method 40 further comprises attaching the second lead to thesubstrate (46). The attaching can be performed in a manner similar tothat as the attaching of the first lead with the first contact pad. Insome implementations, the second lead of the leadframe may be attachedto the substrate concurrently with the first lead of the leadframe beingattached to the semiconductor chip (e.g., such that the first lead andthe second lead are attached to the semiconductor chip and thesubstrate, respectively, during a same process step).

In some implementations, the first and second leads may be included in asingle leadframe that is attached to one or more semiconductor chippackages (e.g., such that all leads of the leadframe are connected whenattached to the one or more semiconductor chip packages). In such acase, after the one or more semiconductor chip packages areencapsulated, as described below, the leadframe may be trimmed (e.g.,such that at least the first leads and the second leads are no longerconnected).

The method 40 further comprises disposing an encapsulant on thesubstrate, the first semiconductor chip, and the leadframe (47). In someimplementations, the encapsulant may be disposed using compressionmolding, transfer molding, injection molding, and/or the like.

According to an example of the method 40, connecting the first andsecond leads with the first contact pad and with the first metalliclayer of the substrate, respectively, is performed concurrently, asdescribed above.

According to an example of the method 40, the method further comprisesproviding a second semiconductor chip having a third surface (e.g., anupper main face) and a fourth surface (e.g., a lower main face),disposing the second semiconductor chip on the substrate, and attachingthe first lead to the fourth surface of the second semiconductor chip.In some aspects, the second semiconductor chip can be diode chip (e.g.,wherein a first contact pad is an anode contact pad and a second contactpad is a cathode contact pad). According to a further example thereof,attaching the first lead to the second semiconductor chip, attaching thefirst lead to the first semiconductor chip, and attaching the secondlead to the substrate, may be performed concurrently. Such examples willbe shown in somewhat more detail further below.

Although FIG. 4 shows example blocks of method 40, in someimplementations, method 40 may include additional blocks, fewer blocks,different blocks, or differently arranged blocks than those depicted inFIG. 4. Additionally, or alternatively, two or more of the blocks ofmethod 40 may be performed in parallel.

FIGS. 5A-5F show schematic cross-sectional side view representationsassociated with an example 50 of the method 40 for fabricating asemiconductor chip package.

According to FIG. 5A, a substrate 51 is provided, wherein substrate 51comprises an insulator layer 51A, a first upper metallic layer 51B, anda second lower metallic layer 51C. The substrate 51 can be, for example,a direct bonded copper (DCB), wherein the insulator layer 51A is aceramic-based material, and the first and second metallic layers 51B and51C are copper layers.

According to FIG. 5B, solder layers 51B1 of a first solder materialcomprising a first melting point of, for example 300° C., are appliedonto the first metallic layer 51B at positions at which the first andsecond semiconductor chips are to be attached.

According to FIG. 5C, first and second semiconductor chips 52 and 55 areattached to the substrate. For example, the first and secondsemiconductor chips 52 and 55 may be soldered on the solder layers 51B1by a reflow process that includes applying a temperature that is higherthan the first melting temperature and, thereafter, cooling down. Thefirst semiconductor chip 52 can, for example, be an IGBT chip that isconnected with its collector contact pad on its lower main face to thesolder layer 51B1, and the second semiconductor chip 55 can, forexample, be a semiconductor diode chip which is connected with its lowerelectrode (anode) contact pad to the solder layer 51B1.

According to FIG. 5D, second solder layers 51B2 are applied onto uppersurfaces of the first and second semiconductor chips 52 and 55. Thesecond solder layers 51B2 are made of a second solder material which isdifferent from the first solder material, in particular which comprisesa second melting point that is lower than the first melting point of thefirst solder material. The second melting point can be, for example,250° C. The second solder layers 51B2 are applied onto the emittercontact pad of the IGBT chip 52 and onto the upper electrode (cathode)pad of the diode chip 55.

According to FIG. 5E, a leadframe 53 comprising one or more first leads53.1 and one or more second leads 53.2 (e.g., as shown in FIGS. 2A-2E,FIGS. 3A and 3B, and/or the like), are attached to the first and secondsemiconductor chips 52 and 55. More specifically, the first leads 53.1comprise three horizontal portions, a first horizontal portion 53.1A atthe right end portion, and second horizontal and third horizontalportions 53.1B and 53.1C wherein the third horizontal portion 53.1C islocated at the left end portion and the second horizontal portion 53.1Bis located in between the first and third horizontal portions 53.1A and53.1C. The second and third horizontal portions 53.1B and 53.1C areplaced onto the second solder layers 51B2 on the upper contact pads ofthe first and second semiconductor chips 52 and 55, and the second leads53.2 are placed onto the second solder layers 51B2 on the first metalliclayer 51B. Then a reflow process is performed by applying a temperatureabove the second melting temperature (but not above the first meltingpoint) followed by a cooling down with the result that the first andsecond leads 53.1 and 53.2 are directly attached to the first and secondsemiconductor chips 52 and 55 and the substrate, respectively.

According to FIG. 5F, an encapsulant 54 is applied to the substrate 51,the first and second semiconductor chips 52 and 55, and the leadframe53.

As indicated above, FIGS. 5A-5F are provided merely as examples. Otherexamples are possible and may differ from what was described with regardto FIGS. 5A-5F.

FIGS. 6A and 6B show a schematic top view representation of asemiconductor chip package 60 and a circuit diagram of an electricalcircuit, respectively, according to another example in which foursemiconductor chips are included in a semiconductor package in order toform a half-bridge circuit.

The semiconductor chip package 60 may comprise a substrate 61 that issimilar to the substrate 21 of the semiconductor chip package 20.However, as shown in FIG. 6A, the substrate 61 may include separateupper metallic layers 61B1 and 61B2 (e.g., rather than a single uppermetallic layer 21B as shown with respect to, for example, thesemiconductor chip package 20) that are electrically isolated from eachother. As shown in FIG. 6A, the semiconductor chip package 60 furthercomprises a first semiconductor chip 62A (e.g., a first semiconductortransistor chip), a second semiconductor chip 65A (e.g., a firstsemiconductor diode chip), a third semiconductor chip 62B (e.g., asecond semiconductor transistor chip), and a fourth semiconductor chip65B (e.g., a second semiconductor diode chip), each of which can beattached to the substrate 61.

The semiconductor chip package 60 further comprises a leadframe 63comprising a first lead 63.1, a second lead 63.2, a third lead 63.3 anda fourth lead 63.4. In some implementations, one or more of the firstlead 63.1, the second lead 63.2, the third lead 63.3, and/or the fourthlead 63.4 may include separate (e.g., parallel) leads, as describedabove. As shown, the first lead 63.1 is attached to the firstsemiconductor chip 62A and the second semiconductor chip 65A. As shown,the second lead 63.2 is attached to the first upper metallic layer 61B1of the substrate 61. As further shown, the third lead 63.3 is attachedto the third semiconductor chip 62B and the fourth semiconductor chip65B. As shown, the fourth lead 63.4 is attached to the first uppermetallic layer 61B2 of the substrate 61. In some implementations, asshown in FIG. 6A, the first lead 63.1 is connected to the fourth lead63.4 in order to form a half-bridge circuit between the firstsemiconductor chip 62A, the second semiconductor chip 65A, the thirdsemiconductor chip 62B, and the fourth semiconductor chip 65B. In someimplementations, the first lead 63.1 may be connected to the fourth lead63.4 within the semiconductor chip package 60, as shown in FIG. 6A.Alternatively, the first lead 63.1 may be connected to the fourth lead63.4 outside of the semiconductor chip package 60.

Here, the first semiconductor chip 62A, the second semiconductor chip65A, the third semiconductor chip 62B, and the fourth semiconductor chip65B are electrically connected in parallel between the first lead 63.1,the second lead 63.2, the third lead 63.3, and the fourth lead 63.4. Ifthe first semiconductor chip 62A is a first semiconductor transistorchip, the second semiconductor chip 65A is a first semiconductor diodechip, the third semiconductor chip 62B is a second semiconductortransistor chip, and the fourth semiconductor chip 65B is asemiconductor diode chip, then a circuit configuration is provided whichis depicted in the circuit diagram of FIG. 6B. The circuit diagram showsthe transistor 62A (e.g., included in the first semiconductor transistorchip 62A) connected in parallel with the diode 65A (e.g., included inthe first semiconductor diode chip 65A), and the transistor 62B (e.g.,included in the second semiconductor transistor chip 62B) connected inparallel with the diode 65B (e.g., included in the second semiconductordiode chip 65B). In some implementations, the diodes 65A and 65B areprovided to protect the transistors 62A and 62B against unwanted andunintentionally occurring peak voltages.

In cross section, the connections between the elements may be similar tothose as described above in connection with the semiconductor chippackage 20. Further, in some implementations, the first lead 63.1, thesecond lead 63.2, the third lead 63.3, and the fourth lead 63.4 compriseparticular shapes that allow them to be connected to the respectivesemiconductor chips in the manner described above.

The number, arrangement, thicknesses, and/or the like, of layers andelements shown in FIGS. 6A and 6B are provided as examples. In practice,the semiconductor chip package 60 may include additional layers and/orelements, fewer layers and/or elements, different layers and/orelements, or differently arranged layers and/or elements than thoseshown in FIGS. 6A and 6B.

FIGS. 7A and 7B show a schematic top view representation and a schematiccross-sectional side view representation, respectively, of an exampleelectronic module 700 that comprises six semiconductor chip packages, asdescribed herein.

The cross-sectional side view representation as shown in FIG. 7B, hasbeen taken along a plane indicated by line B-B in FIG. 7A.

FIG. 7A shows an electronic module 700 in a top view representation. Theelectronic module 700 comprises six semiconductor chip packages 70 eachof which may comprise a structure of a semiconductor chip package asdescribed herein. For purposes of clarity, only some elements of thesemiconductor chip package 70 are shown in FIG. 7B. Here the substrate71 can be similar to the substrates 11, 21, 31, and 51 of the previousexamples, the first semiconductor chip 72 can be similar to the firstsemiconductor chips 12, 22, 32, and 52 of the previous examples, and thefirst lead 73.1 can be similar to the first leads 13.1, 23.1, 33.1, and53.1 of the previous examples.

In some implementations, the semiconductor chip packages 70 can beelectrically connected with each other. For example, when looking atFIG. 7A, it can be the case that each two semiconductor chip packages 70(e.g., arranged laterally adjacent to each other) can be connected inorder to form a half-bridge circuit. Thus, in some implementations, theelectronic module 700 may comprise three half-bridge circuits. Such anelectronic module 700 can be used, for example, for driving a 3-phasemotor.

In some implementations, the backside of the electronic module 700 canbe actively cooled. In particular, the semiconductor chip packages 70can be mounted on a cooling substrate 710 which can be, for example, ahollow metallic cooling box via which a cooling medium is to flow.

The number, arrangement, thicknesses, and/or the like, of layers,elements, and semiconductor chip packages shown in FIGS. 7A and 7B areprovided as examples. In practice, the electronic module 700 may includeadditional layers, elements, and/or semiconductor chip packages, fewerlayers, elements, and/or semiconductor chip packages, different layers,elements, and/or semiconductor chip packages, or differently arrangedlayers, elements, and/or semiconductor chip packages than those shown inFIGS. 7A and 7B.

In some implementations, a semiconductor chip package may include asemiconductor chip disposed on a substrate, wherein the semiconductorchip has a first surface and a second surface, and wherein the firstsurface of the semiconductor chip is connected to the substrate; and aleadframe that includes a first lead and a second lead, wherein thefirst lead of the leadframe is directly attached to the second surfaceof the semiconductor chip, and wherein the second lead of the leadframeis directly attached to the substrate.

In some implementations, the semiconductor chip is a power switch.

In some implementations, the first lead includes at least two leads thatare aligned along substantially parallel directions.

In some implementations, the second lead includes at least two leadsthat are aligned along substantially parallel directions.

In some implementations, the semiconductor chip is a first semiconductorchip and a first portion of the first lead is directly attached to thesecond surface of the first semiconductor chip, and wherein thesemiconductor chip package further comprises a second semiconductor chiphaving a third surface and a fourth surface, wherein the third surfaceof the second semiconductor chip is connected to the substrate, andwherein a second portion of the first lead is directly attached to thefourth surface of the second semiconductor chip.

In some implementations, the first semiconductor chip is a transistorand the second semiconductor chip is a diode, wherein the diode iselectrically connected in parallel with the transistor.

In some implementations, a third portion of the first lead extends belowthe second and fourth surfaces towards the substrate.

In some implementations, the semiconductor chip package furthercomprises a third semiconductor chip having a fifth surface and a sixthsurface, wherein the fifth surface of the third semiconductor chip isconnected to the substrate, and wherein a third portion of the firstlead is directly attached to the sixth surface of the thirdsemiconductor chip.

In some implementations, the first semiconductor chip is a firsttransistor, the second semiconductor chip is a second transistor, andthe third semiconductor chip is a diode, wherein the first transistor isconnected in parallel with the second transistor and the diode, andwherein the second transistor is connected in parallel with the diode.

In some implementations, the first surface of the first semiconductorchip, the second lead, and the third surface of the second semiconductorchip are connected to a first portion of the substrate, and wherein thesemiconductor chip package further comprises: a third semiconductor chiphaving a fifth surface and a sixth surface, wherein the fifth surface ofthe third semiconductor chip is connected to a second portion of thesubstrate, wherein a first portion of a third lead of the leadframe isdirectly attached to the sixth surface of the third semiconductor chip;and a fourth semiconductor chip having a seventh surface and an eighthsurface, wherein the seventh surface of the fourth semiconductor chip isconnected to the second portion of the substrate, wherein a secondportion of the third lead is directly attached to the eighth surface ofthe fourth semiconductor chip, wherein the first portion of thesubstrate and the second portion of the substrate are electricallyisolated from each other.

In some implementations, a fourth lead of the leadframe is directlyattached to the second portion of the substrate, wherein the fourth leadis connected to the first lead.

In some implementations, the first semiconductor chip is a firsttransistor, the second semiconductor chip is a first diode, the thirdsemiconductor chip is a second transistor, and the fourth semiconductorchip is a second diode, wherein the first transistor is electricallyconnected in parallel with the first diode, and wherein the secondtransistor is electrically connected in parallel with the second diode.

In some implementations, the first semiconductor chip, the secondsemiconductor chip, the third semiconductor chip, and the fourthsemiconductor chip are connected to form a half-bridge circuit.

In some implementations, a method for fabricating a semiconductor chippackage may include disposing a semiconductor chip on a substrate,wherein the semiconductor chip has a first surface and a second surface,and wherein the first surface of the semiconductor chip is connected tothe substrate; attaching a first lead of a leadframe to the secondsurface of the semiconductor chip; and attaching second lead of theleadframe to the substrate.

In some implementations, the method may include disposing an encapsulanton the substrate, the semiconductor chip, and a portion of theleadframe.

In some implementations, at least one of the first lead and the secondlead includes at least two leads that are aligned along substantiallyparallel directions.

In some implementations, the first lead of the leadframe is attached tothe second surface of the semiconductor chip concurrently with thesecond lead of the leadframe being attached to the substrate.

In some implementations, the semiconductor chip is a power switch.

In some implementations, the semiconductor chip is a first semiconductorchip and a first portion of the first lead is attached to the secondsurface of the first semiconductor chip, and wherein the method furthercomprises: disposing a second semiconductor chip on the substrate,wherein the second semiconductor chip has a third surface and a fourthsurface, and wherein the third surface of the semiconductor chip isconnected to the substrate; and attaching a second portion of the firstlead to the fourth surface of the second semiconductor chip.

In some implementations, an electronic module may include at least onesemiconductor chip package comprising: a semiconductor chip disposed ona substrate, wherein a first surface of the semiconductor chip isconnected to the substrate; and a leadframe that includes a first leadand a second lead, wherein the first lead of the leadframe is directlyattached to a second surface of the semiconductor chip, and wherein thesecond lead of the leadframe is directly attached to the substrate.

While the disclosure has been illustrated and described with respect toone or more implementations, alterations and/or modifications may bemade to the illustrated examples without departing from the spirit andscope of the appended claims. In particular regard to the variousfunctions performed by the above described components or structures(assemblies, devices, circuits, systems, etc.), the terms (including areference to a “means”) used to describe such components are intended tocorrespond, unless otherwise indicated, to any component or structurewhich performs the specified function of the described component (e.g.,that is functionally equivalent), even though not structurallyequivalent to the disclosed structure which performs the function in theherein illustrated exemplary implementations of the disclosure. Theforegoing disclosure provides illustration and description, but is notintended to be exhaustive or to limit the implementations to the preciseform disclosed. Modifications and variations are possible in light ofthe above disclosure or may be acquired from practice of theimplementations.

The foregoing disclosure provides illustration and description, but isnot intended to be exhaustive or to limit the implementations to theprecise form disclosed. Modifications and variations are possible inlight of the above disclosure or may be acquired from practice of theimplementations.

Even though particular combinations of features are recited in theclaims and/or disclosed in the specification, these combinations are notintended to limit the disclosure of possible implementations. In fact,many of these features may be combined in ways not specifically recitedin the claims and/or disclosed in the specification. Although eachdependent claim listed below may directly depend on only one claim, thedisclosure of possible implementations includes each dependent claim incombination with every other claim in the claim set.

No element, act, or instruction used herein should be construed ascritical or essential unless explicitly described as such. Also, as usedherein, the articles “a” and “an” are intended to include one or moreitems, and may be used interchangeably with “one or more.” Furthermore,as used herein, the term “set” is intended to include one or more items(e.g., related items, unrelated items, a combination of related andunrelated items, etc.), and may be used interchangeably with “one ormore.” Where only one item is intended, the term “one” or similarlanguage is used. Also, as used herein, the terms “has,” “have,”“having,” or the like are intended to be open-ended terms. Further, thephrase “based on” is intended to mean “based, at least in part, on”unless explicitly stated otherwise.

1. A semiconductor chip package, comprising: a semiconductor chipdisposed on a substrate, wherein the semiconductor chip has a firstsurface and a second surface, and wherein the first surface of thesemiconductor chip is connected to the substrate; and a leadframe thatincludes a first lead and a second lead, wherein the first lead of theleadframe is directly attached to the second surface of thesemiconductor chip, and wherein the second lead of the leadframe isdirectly attached to the substrate.
 2. The semiconductor chip package ofclaim 1, wherein the semiconductor chip is a power switch.
 3. Thesemiconductor chip package of claim 1, wherein the first lead includesat least two leads that are aligned along substantially paralleldirections.
 4. The semiconductor chip package of claim 1, wherein thesecond lead includes at least two leads that are aligned alongsubstantially parallel directions.
 5. The semiconductor chip package ofclaim 1, wherein the semiconductor chip is a first semiconductor chipand a first portion of the first lead is directly attached to the secondsurface of the first semiconductor chip, and wherein the semiconductorchip package further comprises a second semiconductor chip having athird surface and a fourth surface, wherein the third surface of thesecond semiconductor chip is connected to the substrate, and wherein asecond portion of the first lead is directly attached to the fourthsurface of the second semiconductor chip.
 6. The semiconductor chippackage of claim 5, wherein the first semiconductor chip is a transistorand the second semiconductor chip is a diode, wherein the diode iselectrically connected in parallel with the transistor.
 7. Thesemiconductor chip package of claim 5, wherein a third portion of thefirst lead extends below the second and fourth surfaces towards thesubstrate.
 8. The semiconductor chip package of claim 5, wherein thesemiconductor chip package further comprises a third semiconductor chiphaving a fifth surface and a sixth surface, wherein the fifth surface ofthe third semiconductor chip is connected to the substrate, and whereina third portion of the first lead is directly attached to the sixthsurface of the third semiconductor chip.
 9. The semiconductor chippackage of claim 8, wherein the first semiconductor chip is a firsttransistor, the second semiconductor chip is a second transistor, andthe third semiconductor chip is a diode, wherein the first transistor isconnected in parallel with the second transistor and the diode, andwherein the second transistor is connected in parallel with the diode.10. The semiconductor chip package of claim 5, wherein the first surfaceof the first semiconductor chip, the second lead, and the third surfaceof the second semiconductor chip are connected to a first portion of thesubstrate, and wherein the semiconductor chip package further comprises:a third semiconductor chip having a fifth surface and a sixth surface,wherein the fifth surface of the third semiconductor chip is connectedto a second portion of the substrate, wherein a first portion of a thirdlead of the leadframe is directly attached to the sixth surface of thethird semiconductor chip; and a fourth semiconductor chip having aseventh surface and an eighth surface, wherein the seventh surface ofthe fourth semiconductor chip is connected to the second portion of thesubstrate, wherein a second portion of the third lead is directlyattached to the eighth surface of the fourth semiconductor chip, whereinthe first portion of the substrate and the second portion of thesubstrate are electrically isolated from each other.
 11. Thesemiconductor chip package of claim 10, wherein a fourth lead of theleadframe is directly attached to the second portion of the substrate,wherein the fourth lead is connected to the first lead.
 12. Thesemiconductor chip package of claim 10, wherein the first semiconductorchip is a first transistor, the second semiconductor chip is a firstdiode, the third semiconductor chip is a second transistor, and thefourth semiconductor chip is a second diode, wherein the firsttransistor is electrically connected in parallel with the first diode,and wherein the second transistor is electrically connected in parallelwith the second diode.
 13. The semiconductor chip package of claim 10,wherein the first semiconductor chip, the second semiconductor chip, thethird semiconductor chip, and the fourth semiconductor chip areconnected to form a half-bridge circuit.
 14. A method for fabricating asemiconductor chip package, the method comprising: disposing asemiconductor chip on a substrate, wherein the semiconductor chip has afirst surface and a second surface, and wherein the first surface of thesemiconductor chip is connected to the substrate; attaching a first leadof a leadframe to the second surface of the semiconductor chip; andattaching second lead of the leadframe to the substrate.
 15. The methodof claim 14, further comprising disposing an encapsulant on thesubstrate, the semiconductor chip, and a portion of the leadframe. 16.The method of claim 14, wherein at least one of the first lead and thesecond lead includes at least two leads that are aligned alongsubstantially parallel directions.
 17. The method of claim 14, whereinthe first lead of the leadframe is attached to the second surface of thesemiconductor chip concurrently with the second lead of the leadframebeing attached to the substrate.
 18. The method of claim 14, wherein thesemiconductor chip is a power switch.
 19. The method of claim 14,wherein the semiconductor chip is a first semiconductor chip and a firstportion of the first lead is attached to the second surface of the firstsemiconductor chip, and wherein the method further comprises: disposinga second semiconductor chip on the substrate, wherein the secondsemiconductor chip has a third surface and a fourth surface, and whereinthe third surface of the semiconductor chip is connected to thesubstrate; and attaching a second portion of the first lead to thefourth surface of the second semiconductor chip.
 20. An electronicmodule, comprising: at least one semiconductor chip package comprising:a semiconductor chip disposed on a substrate, wherein a first surface ofthe semiconductor chip is connected to the substrate; and a leadframethat includes a first lead and a second lead, wherein the first lead ofthe leadframe is directly attached to a second surface of thesemiconductor chip, and wherein the second lead of the leadframe isdirectly attached to the substrate.